1. Field of the Invention
The invention relates to a method of fabricating semiconductors, and more particularly to a method of fabricating a bit line to reduce the contact resistance thereof.
2. Description of the Related Art
To fabricate a dynamic random access memory (DRAM), a fourth polysilicon layer and a tungsten silicide layer are normally in use as a bit line (BL) to reduce the resistance thereof and to improve the working speed. However, due to the poor step coverage of the tungsten silicide layer, the aspect ratio of DRAM is big, and therefore, the contact between tungsten silicide and the fourth polysilicon layer is incomplete.
The conventional way to improve the contact problem is to use di-cholo-silane to replace silane. A tungsten silicide layer is formed with an improved step coverage by using chemical vapor deposition. However, the step height of the contact window is still as high as 10 K.ANG., so that the contact problem between the tungsten silicide and the fourth polysilicon layer cannot be solved effectively.
Referring to FIGS. 1A to FIG. 1F, a cross-sectional view of the fabrication flow of a bit line is shown.
In FIG. 1A, a semiconductor substrate 10 is provided. A source/drain region 9 is formed in the substrate 10. Over the substrate 10, a field oxide layer 11, a first polysilicon layer 12, and a spacer 13 are formed in sequence. The first polysilicon layer 12 is formed by a stack layer of a doped polysilicon layer 16, a tungsten silicide 15, and a silicon nitride layer 14. A TEOS oxide having a thickness of about 1.5 K.ANG. is formed by low pressure chemical vapor deposition (LPCVD) and covers the field oxide layer 11, the first polysilicon layer 12, and the spacer 13. Using photolithography and etching to define the TEOS oxide, a first oxide layer 17 is formed in a specific region to expose the source/drain region 9 on the substrate 10.
Referring to FIG. 1B, a 5 K.ANG. thick polysilicon layer which is doped with dopant to increase the conductivity is formed and covers the exposed source/drain region 9 and the first oxide layer 17. A hemispherical silicon grain (HSG) layer is formed on the polysilicon layer. Using photolithography and etching, the polysilicon layer and the hemispherical silicon grain layer are defined to form a second polysiticon layer 18 and a hemishperical silicon grain layer 19. These two layers 18 and 19 are the bottom electrode of the DRAM.
Referring to FIG. 1C, a dielectric layer is formed and covers the exposed hemispherical silicon grain layer 19 and the second polysilicon layer 18. The dielectric layer is a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer, or a tantalum oxide/titanium oxide layer. The polysilicon layer is doped with dopant to increase the conductivity. Using photolithography and etching to define the polysilicon layer and the dielectric layer, a third polysilicon layer 21 and a dielectric layer 20 are formed. The third polysilicon layer is used as a top electrode of the DRAM.
Referring to FIG. 1D, a second oxide layer 22, a BPSG layer 23 are formed and cover the third polysilicon layer 21 by atmosphere pressure chemical vapor deposition (APCVD). The thickness of the second oxide layer 22 is about 1.5 K.ANG., and it is about 7.5 K.ANG. for the BPSG layer 23.
Referring to FIG. 1E, using photolithography and etching to define the BPSG layer 23, the first oxide layer 17, and the second oxide layer 22, a contact window 24 are formed, and the source/drain region 9 of the substrate 10 is exposed.
Referring to FIG. 1F, a fourth polysilicon layer 25 having a thickness of about 1 K.ANG. is formed and covers the BPSG layer 23 and the contact window 24. The fourth polysilicon layer 25 is doped with dopant to increase the conductivity. A tungsten silicide (WSi.sub.x) layer 26 is formed and covers the fourth polysilicon layer 25. The tungsten silicide layer 26 is formed by LPCVD with reactant gases such as tungsten flouride and tungsten reacted with silane (SiH.sub.4) at about 300.degree. C. to 400.degree. C. The bit line is composed by the fourth polysilicon layer 25 and the tungsten silicide layer 26.
However, since the tungsten silicide cannot fill the whole contact window 24, the contact between the tungsten silicide 26 and the fourth polysilicon layer 25 is incomplete. Therefore, the contact resistance of the bit line is increased. Moreover, the reflection coefficient of tungsten silicide is so high that a necking phenomenon is likely to happen while coating photoresist.